1. Field of the Invention
The present invention relates to a microcomputer and associated method, and more particularly, to a microcomputer and associated method for reducing memory usage of the microcomputer.
2. Description of the Prior Art
With advances of integrated circuit technology, more and more microcomputer systems are used to assist the operations of devices, such as cell phones, air conditioners, scanners, routers, etc. However, in contrast to personal computer systems, microcomputer systems have fewer transistors, and so their related power consumption is less. Furthermore, the design of microcomputers is relatively simple, so their applications have more potential for variety than personal computer systems. Microcomputer systems are generally designed to provide users with great flexibility when setting up their systems. Microcomputer systems are designed to permit users to setup a storage device to store settings. Of various storage devices, flash memory is often used as the storage device of a microcomputer system due to the nonvolatile nature of flash memory, and due to their stability in operating. Flash memory in a microcomputer system is used to store programs that control the microcomputer system, such as boot programs, flash memory drivers, etc. The flash memory driver is used to control the writing of data into the flash memory. In particular, flash memory has a limitation in that when data is written into the flash memory, data cannot be read from the flash memory. Attempting to read and write data from the flash memory at the same time may lead to corruption of data within the flash memory. However, when the microcomputer system executes the flash memory driver to write data into the flash memory, program code for the flash memory driver must be read to execute the writing of data. This, of course, cannot be permitted. So, to ensure the accuracy of writing data, the prior art microcomputer system copies all programs in the flash memory to another storage device, and then reads from that storage device to execute the flash memory driver so as to avoid the above-mentioned problem.
Please refer to FIG. 1. FIG. 1 is a block diagram of a prior art microcomputer 10. The microcomputer 10 is used by network data equipment, such as model FCD E320/E321 of Acer Communications & Multimedia Inc.® (now known as BenQ Corp.®). It comprises a central processing unit (CPU) 12 to control operations of the microcomputer 10, a first chip 16 with a flash memory 26, a second chip 14 with a memory 24, an address bus 18 for delivering memory address signals, and a data bus 22 for delivering data stored in the flash memory 26 and the memory 24. The flash memory has a system program 28 for controlling operations of the microcomputer 10, a data file 36 for storing settings of the microcomputer 10, and a flash memory driver 32 for controlling operations of the flash memory 26 so that data can be written into the data file 36. The memory 24 is a volatile memory, such as dynamic random access memory (DRAM). The processor 12 can temporarily store data in the memory 24.
When the microcomputer system 10 starts, the processor 12 loads the system program 28 and the flash memory driver 32 in the flash memory 26 into the memory 24. Please refer to FIG. 2. FIG. 2 is a memory map of the memory 24 and flash memory 26 of FIG. 1. As shown in FIG. 2, the flash memory 26 has an address space from 0x80000 to 0xFFFFF, and the memory 24 has an address space from 0x00000 to 0x7FFFF. The flash memory driver 32 is stored in memory from 0x80400 to 0x8FFFF, which is in the flash memory 26. The system program 28 is stored in memory from 0x90000 to 0xF7FFF, which is in the flash memory 26. The data file 36 is stored in the flash memory 26 from 0xF8000 to 0xFAFFF. When the microcomputer 10 begins operation, the processor 12 loads all programs (e.g. the system program 28 and the flash memory driver 32, etc.) in the flash memory 26 into the memory 24. As shown in FIG. 2, the processor 12 loads the system program 28 into the memory 24 located in the address of 0x10000 to 0x77FFF, and loads the flash memory driver 32 into the memory 24 from 0x00400 to 0x0FFFF. When the processor 12 executes program code, the processor 12 reads from the address space corresponding to the memory 24. Consequently, when the processor 12 executes the flash memory driver 32 to write data into the data file 36 of the flash memory 26, the processor 12 reads program code for the flash memory driver 32 from the memory address area 0x00400˜0x0FFFF. In this manner, the microcomputer 10 does not need to read program code for the flash memory driver 32 from the flash memory 26 when writing data into the data file 26, and the accuracy of data writing into the flash memory 26 is ensured. However, because the processor 12 loads all code in the flash memory 26 into the memory 24, when the flash memory 26 has more program codes, the microcomputer 10 must be equipped with a larger total memory capacity.